Hybrid built-in self-test and test generation techniques for by Gert Jervan. PDF

By Gert Jervan.

ISBN-10: 9185297976

ISBN-13: 9789185297979

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Extra resources for Hybrid built-in self-test and test generation techniques for digital systems

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17. Other possibilities include off-chip source/sink or combination of the previous ones. In case of the off-chip source/sink, external ATE is needed. On the other hand, on-chip test structures occupy additional silicon area, so there is no clear answer what kind of implementation to choose. The final implementation decision is influenced by three different factors: type of circuitry in the core, predefined test set provided by the core provider and requirements for test time, quality and cost.

On the other hand, on-chip test structures occupy additional silicon area, so there is no clear answer what kind of implementation to choose. The final implementation decision is influenced by three different factors: type of circuitry in the core, predefined test set provided by the core provider and requirements for test time, quality and cost. 50 TESTING AND DESIGN FOR TESTABILITY Test Access Mechanism The test access mechanism (TAM) is used to transfer the test data from the test pattern source to the core under test and from the core under test to the test pattern sink.

By embedding different test activities on-chip makes it possible to use an ATE with significantly reduced requirements. Those methods are in general known as DFT techniques and are described in greater length later in this chapter. 2. Abort-on-First-Fail Testing In a production test environment, where a large number of chips have to be tested, an abort-on-first-fail (AOFF) approach is usu- 29 CHAPTER 2 ally utilized. It means that the test process is stopped as soon as a fault is detected. This approach leads to reduced test times and consequently to reduced production costs, as faulty chips can be eliminated before completing the entire test flow.

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